I am so glad to team up with my engineers Sanjay and Abhilash, our Mavenites, as a verification consultant and drive the UVM engagement with our customer. We are architecting the complete verification environment using UVM methodology. This environment is composed of multiple UVCs and functional models. The DUV is very complex one. Its really challengable to model the complete environment in which usually the DUV would be used.
Its a rare opportunity for young verification engineers like Sanjay and Abhilash. They are part of initial planning phase too and exploring TB architecture and verification planning and management process.
Sanjay and Abhilash have done VLSI-RN course at Maven Silicon. They have joined in our services organization, Aceic Design Technologies as Project Engineer - ASIC Verification and worked on multiple IP core verification projects. Today they are working on cutting edge technologies and growing as verification specialists.
What Abhilash says about our VLSI Training at Maven Silicon
Regards
Siva
CEO, Maven Silicon
Its a rare opportunity for young verification engineers like Sanjay and Abhilash. They are part of initial planning phase too and exploring TB architecture and verification planning and management process.
Sanjay and Abhilash have done VLSI-RN course at Maven Silicon. They have joined in our services organization, Aceic Design Technologies as Project Engineer - ASIC Verification and worked on multiple IP core verification projects. Today they are working on cutting edge technologies and growing as verification specialists.
What Abhilash says about our VLSI Training at Maven Silicon
Regards
Siva
CEO, Maven Silicon
