Chip design process goes through various transformations and get you the final product. One needs to understand all the steps of the VLSI design flow when he begins his career in any semiconductor industry.
This is a detailed document that defines the product functionality and features. It’s a golden reference to the complete design team. Let us say you are designing mobile chip. The spec of this chip has the details like, tele conference, email support, audio and video, built-in camera, games, etc.
Design team drafts one more document called design specification before capturing the Register Transfer Level logics in HDLs. This design specification has all the details that are needed for the hardware design, such as design architecture, RTL block diagram, clock frequency, waveforms, clock domain details, port details, design partition details etc.
One can't easily become RTL designer just by learning HDLs. You need to learn RTL coding style from the experienced designers.
Verification team drafts an another document called verification plan. This verification plan have all the details needed for the verification, such as TB architecture, coverage models, list of key features to be verified etc. In this verification process, RTL functionality is simulated and verified whether it behaves as per the product specification.
Most of the ASIC re-spins are due to the functional bugs. Verification process is not yet completely automated and its more time consuming than the design implementation process. 70% of the design cycle time is consumed by the verification.
Refer my blog Verification Sigin-off at
The verified RTL is synthesized into Gate Level Netlist. This process is completely automated with the help of EDA tools. But still one needs to be good at HDL based design implementation to understand the reports generated by the Synthesizer and explain to the design team about the synthesis related issues.
Place and Route
The netlist is basically a list of primitives. All the primitives are placed and connected to form the chip layout. The P&R process is also completely automated. But still one needs to understand the tool very well and try different routing algorithms to implement the design effectively on to the chip.
The P&R process produces a binary file as output. This binary data will be used to configure the FPGA. The configured FPGA implements the design functionality.
Finally the routed netlist that is called as GDS-II will be sent to the foundry that manufactures the chip as per the technology requirement