Tuesday, February 3, 2009

Challenge the Economic Recession

Everybody is scared of this economic recession. Industries are not doing well in this downturn. Most of the industries stopped recruiting even experienced engineers. Newspaper stories of Layoffs and Pink Slips threaten us further.

How are you going to face this industry downturn?

I am sure you will try sincerely to get into industry. You will keep on applying to the companies. But in this situation industries might hesitate to consider fresher. If this continues for some time, you would get frustrated and lose your confidence. You may even start thinking of changing your career too. I am not trying to threaten you by exaggerating the current situation. It's natural and the market condition always goes through peaks and slowdowns in a cyclic fashion. So you can't do anything just by worrying about the economic recession. You should plan very carefully how to face it.

Do you want to be idle till this situation becomes normal?

Time is GOLD. I suggest you to utilize this time very usefully. Do some specialized trainings and increase your skill sets. But you need to choose the training institution very carefully. Find out, whether they are really capable of guiding you to do the industry standard projects on your own. The projects that you do will increase the value of your resume. This way you can make yourself ready and face the interviews when the industries start recruiting.

Be positive. Challenge this economic down turn and show to this world who you are... All the best!

You can reach me directly at guru.vlsitech@gmail.com for any help or information that you may require regarding VLSI career,VLSI training institutions etc ..

Monday, February 2, 2009

What is SystemVerilog?

Let us first understand what is Systemverilog [SV]. SV is not something like a brand new hardware verification language. It's built on top of Verilog HDL. All the Verilog language constructs seamlessly work with SV and vice-versa. In common man terms, one can say SystemVerilog is the latest version of Verilog HDL.

Why we need this language?
Basically HDLs are meant for RTL description of the design and they are not good for verification. Some engineers wrongly assume that Verilog is good for verification and VHDL is good for RTL. Actually both HDLs lack many constructs that you need for complex chip level verification.

Usually verification engineers use Hardware Verification Languages [HVLs] like e, Vera to implement the testbenches. RTL designers use HDLs , Verilog or VHDL for the design implementation and SVA/PSL for the assertions. So one needs to learn multiple languages to manage the complete front-end design process.

SystemVerilog is the language that supports everything you need for RTL implementation and verification as well. Being an SV expert, one can easily become front-end designer/verification engineer.

You can directly reach me at guru.vlsitech@gmail.com to know more about SystemVerilog ... VLSI training institutions etc .