When your friends talk about any chip design course, you might think it’s for ECE/EEE engineers and not for CSE/IT engineers who want to become great software programmers. If you are a CSE/IT engineer, you probably move away from that discussion.
If you have an assumption that VLSI design course is only for the electronics engineers, you really need to change your mind set. A good C/C++ programmer who has good knowledge in digital fundamentals can easily become a verification engineer. You will be excited when you understand how we really verify the complex chips. Let me brief how we make use of the software concepts to verify the chip.
Hardware designers use Hardware Description Language [HDL] for designing the chips. But the verification engineers use Hardware Verification Languages [HVL] for verifying the chips. Testbench is the program that generates stimuli to the design and verifies the functionality of the same. Trust me, writing HVL based testbench is very similar to C++ programming.
At present SystemVerilog is the standard HVL that is becoming prominent in the verification world. This language is completely based on object oriented programming [OOP] concepts. We verification engineers use all the software concepts like Object Oriented Programming, Polymorphism, and Inheritance etc. to architect the testbenches.
Software execution is completely sequential but hardware programs execute concurrently too. Hardware designers always think in terms of digital logics like flip-flops, multiplexors, etc. Their programming style is entirely different from software programming. One needs to have verification mind set and think like a software programmer to write effective testbenches. So industries prefer software engineers to verify the complex chips, especially for writing the testbenches using latest verification technologies.
You can refer my blog "Functional Verification" at
http://vlsi-verification.blogspot.com to explore more on verification concepts and technologies.