Why you need to learn SystemVerilog?

In VLSI industries, everybody talks about SystemVerilog [SV]. We also find lot of job opportunities for the verification engineers who have working knowledge in SV. Students also look out for the VLSI design courses that focus more on verification and SV. They also strongly believe that SV knowledge is highly needed to get into industries.

Why so much noise about SystemVerilog? What is happening in the verification world?

I still remember, few years back everybody was talking about the hardware verification language 'e' and Specman. Industries used to search for the strings "e" and "Specman" in the resume. Cadence also acquired Versity to increase their market share in the verification. But now the VLSI industries are moving towards SV and migrating their legacy testbenches from the proprietary HVLs and HDLs to SV.

This change in the verification community clearly indicates that you always need to update yourself on the latest technology to maintain your market value, whether you are a student or an experienced verification engineer.