Let us first understand what is Systemverilog [SV]. SV is not something like a brand new hardware verification language. It's built on top of Verilog HDL. All the Verilog language constructs seamlessly work with SV and vice-versa. In common man terms, one can say SystemVerilog is the latest version of Verilog HDL.
Why we need this language?
Basically HDLs are meant for RTL description of the design and they are not good for verification. Some engineers wrongly assume that Verilog is good for verification and VHDL is good for RTL. Actually both HDLs lack many constructs that you need for complex chip level verification.
Usually verification engineers use Hardware Verification Languages [HVLs] like e, Vera to implement the testbenches. RTL designers use HDLs , Verilog or VHDL for the design implementation and SVA/PSL for the assertions. So one needs to learn multiple languages to manage the complete front-end design process.
SystemVerilog is the language that supports everything you need for RTL implementation and verification as well. Being an SV expert, one can easily become front-end designer/verification engineer.
You can directly reach me at firstname.lastname@example.org to know more about SystemVerilog ... VLSI training institutions etc .